Verilog

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Verilog

  • The most C-like language
  • Concise in comparison to VHDL

Anatomy of a Verilog Program

  • Here is a module describing a two-input AND gate
1 module and2
2    (
3       input wire a, b, // yup that's supposed to be a comma, not a semi-colon
4       output wire out
5    ); // yup there's supposed to be a semi-colon here...
6 
7    assign out = a & b;
8 
9 endmodule
  • The module gets a name, in this case and2
  • The module gets named and typed interface signals
    • Inputs: internally must always be of type wire, externally the inputs can be connected to a variable of type reg or wire.
    • Outputs: internally can be of type wire or reg, externally the outputs must be connected to a variable of type wire.
    • Inouts: internally or externally must always be type wire, can only be connected to a variable wire type.

Continuous Assignment

  • Simplest way to think of this is that it's assigning a name to a wire (aliasing)
    • Must be preceded by the keyword assign and the associated operator is =
    • In the example there is an implicit net that results from the primitive operation a & b. That result is assigned / aliased to the port out

Non-Blocking Assignment

  • When you build sequential circuits there is generally a clock and registers (i.e. flip-flops) involved.
  • The construct for assigning values to registers is an always block, with a sensitivity list, and the <= operator.
  • Here is a module description for a simple D-flip-flop:
 1 module dff
 2     (
 3         input wire in, clk,
 4         output reg out
 5     );
 6 
 7     always @(posedge clk)
 8         begin
 9            out <= in;
10         end
11 
12 endmodule
  • The behavior this describes is:
    • the input clk is in the sensitivity list
    • whenever (e.g. always @) any signal in the sensitivity list changes in the prescribed way the non-blocking assignments within the always block occur
      • the prescribed way, in this case, is a rising edge (i.e. posedge)
    • In summary, on each rising edge of clk' signal, out samples and holds tbe value of in, and maintains that sampled value until the next rising edge of clk (even if in keeps changing in the interim period)
  • There's no restriction on the number of always blocks a module can contain, nor is there any orthogonality required among sensitivity lists

Selection

  • An analogy to computer programming is the if-elseif-else construct
  • Chained (or not) ternary operators are a common pattern for this e.g. assign out = select ? a : b; would be a basic 2:1 multiplexer
    • When chaining, don't forget the default (else) case or there will be an implied latch
  • More general and expressive description is possible using traditional if / else if / else syntax, but that must be done inside an always block (even if it's a combinational always block), e.g.:
1 always @(*)
2     begin
3        if(select)
4            assign out = a;
5        else
6            assign out = b;
7     end